Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays
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United States of America Patent
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Nov 26, 1991
Issued Date -
N/A
app pub date -
May 15, 1989
filing date -
Oct 7, 1987
priority date (Note) -
Expired
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Abstract
A structure and method for producing mask-configured integrated circuits which are pin compatible substitutes for user-configured logic arrays is disclosed. Mask-defined routing lines having resistive/capacitive characteristics simulating those of user-configurable routing paths in the user-configurable logic array are used in the mask-defined substitutes to replace the user-configurable routing paths. Scan testing networks are formed in the metal-configured substitutes to test the operability of logical function blocks formed on such chips. The scan testing networks comprise a plurality of test blocks each including three field effect pass transistors formed of four adjacent diffusion regions. Proper connection of the gates of these pass transistors to control lines controlling the transistors is tested by transmitting alternating high/low signals through serial conduction paths including the gate electrodes of these transistors.
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