Memory management unit for the MIL-STD 1750 bus
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United States of America Patent
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Jan 7, 1992
Grant Date -
N/A
app pub date -
Oct 25, 1988
filing date -
Oct 25, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A single-chip memory management unit automatically operates in either 1750A or 1750B mode as required, including the provision of memory management and/or block protection, with the added feature of on-chip arbitration between two bus masters that may be either independent of the CPU or controlled by the CPU.
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