ROM and process for producing the same

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United States of America Patent

PATENT NO 5081052
SERIAL NO

07373620

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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MISFET's are formed in the depletion mode in advance in a process comprising blanket implantation of the region in which memory cells are to be formed. MISFET's which are selected from these depletion-mode MISFET's are then formed into enhancement-mode or weak depletion-mode MISFET's to thereby write desired data into the memory cells of a read-only memory. The change of the MISFET's from the depletion mode into the enhancement mode (or weak depletion mode) is effected by introducing an impurity into the channel regions of the selected MISFET's in a manufacturing step that is carried out after the formation of the gate electrodes of the MISFET's.

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Patent Owner(s)

  • HITACHI, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kobayashi, Isamu Tokyo, JP 56 1130
Shibata, Ryuuji Higashiyamato, JP 6 105

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