Method for depositing an insulating layer on a conductive layer of a multi-layer connection board of one very large scale integrated circuit
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United States of America Patent
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Jan 21, 1992
Grant Date -
N/A
app pub date -
Jul 24, 1990
filing date -
Jul 27, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for deposition of an insulating layer on a conductive layer of the multi layer structure of a connection board of a VLSI circuit and a connection board formed by the method. The formation of an insulating layer coplanar with the upper surface of the vias (21) of the conductive layer (16a, 16b) is done by etching of an insulating layer (26) formed of a plurality of successive strata (22, 23, 24, 25) until a surface is obtained that has steps of a maximum height (S4) substantially equal to or less than a desired valve (V) corresponding to the desired degree of planarity of the final insulating layer.
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