A buffer device capable of dealing with multiple priority levels in which the efficiency of the memory capacity utilization can be improved such that the priority levels can be handled at the higher efficiency with smaller memory capacities, and which is adaptable to a high speed buffer implementation. The device includes a data register array containing empty data registers and imaginary FIFO queues, and an adminstrative register array comprised of a two port RAM for storing pointer chains specifying the imaginary FIFO queues. The input of data is accompanied by the modification of the pointer chain to extend it, whereas the output of data is accompanied by the modification of the pointer chain to shorten it, so that the imaginary FIFO queues are administered in flexible manner in order to achieve efficient memory capacity utilization. The procedure for controlling the imaginary FIFO queues can be executed in parallel because of the independency of read and write operations in the two port RAM.
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
This priority date is an estimated earliest
priority date and is purely an estimation. This date should not be
taken as legal conclusion. No representations are made as to the
accuracy of the date listed. Please consult a legal professional
before relying on this date.