US Patent No: 5,086,018

Number of patents in Portfolio can not be more than 2000

Method of making a planarized thin film covered wire bonded semiconductor package

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Abstract

A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY68841

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Conru, H Ward Essex Junction, VT 4 196
Irish, Gary H Jericho, VT 6 236
Pakulski, Francis J Shelburne, VT 3 189
Slattery, William J Essex Junction, VT 4 177
Starr, Stephen G Essex Junction, VT 7 358
Ward, William C Painesville, OH 23 1156

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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (24)
5,256,598 Shrink accommodating lead frame 78 1992
6,271,582 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 5 1997
5,932,485 Method of laser ablation of semiconductor structures 8 1997
6,144,089 Inner-digitized bond fingers on bus bars of semiconductor device package 6 1997
6,148,509 Method for supporting an integrated circuit die 110 1998
6,052,289 Interdigitated leads-over-chip lead frame for supporting an integrated circuit die 7 1998
5,977,616 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 3 1998
6,008,996 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 3 1999
6,344,976 Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die 93 1999
6,524,891 Method of pressure curing for reducing voids in a die attach bondline and applications thereof 1 2000
6,376,282 Inner-digitized bond fingers on bus bars of semiconductor device package 3 2000
6,576,987 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 1 2001
6,710,462 Method of pressure curing for reducing voids in a die attach bondline and applications thereof 1 2001
6,576,993 Packages formed by attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip 8 2001
6,630,732 Lead frames including inner-digitized bond fingers on bus bars and semiconductor device package including same 1 2002
6,624,006 Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip 8 2002
6,693,349 Semiconductor chip package having a leadframe with a footprint of about the same size as the chip 4 2002
7,183,138 Method and apparatus for decoupling conductive portions of a microelectronic device package 1 2003
6,831,353 Interdigitated leads-over-chip lead frame and device for supporting an integrated circuit die 2 2003
7,279,364 Flip-chip adaptor package for bare die 0 2006
7,378,723 Method and apparatus for decoupling conductive portions of a microelectronic device package 1 2006
7,829,991 Stackable ceramic FBGA for high thermal applications 2 2007
8,072,082 Pre-encapsulated cavity interposer 1 2008
8,399,297 Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages 0 2011
 
OVID DATA CO. LLC (23)
5,448,450 Lead-on-chip integrated circuit apparatus 26 1991
5,484,959 High density lead-on-package fabrication method and apparatus 128 1992
5,369,056 Warp-resistent ultra-thin integrated circuit package fabrication method 32 1993
5,369,058 Warp-resistent ultra-thin integrated circuit package fabrication method 32 1994
5,581,121 Warp-resistant ultra-thin integrated circuit package 16 1994
5,702,985 Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method 24 1994
5,572,065 Hermetically sealed ceramic integrated circuit heat dissipating package 94 1994
5,528,075 Lead-on-chip integrated circuit apparatus 40 1995
5,801,437 Three-dimensional warp-resistant integrated circuit module method and apparatus 81 1995
5,654,877 Lead-on-chip integrated circuit apparatus 81 1995
5,864,175 Wrap-resistant ultra-thin integrated circuit package fabrication method 24 1996
5,843,807 Method of manufacturing an ultra-high density warp-resistant memory module 50 1996
5,828,125 Ultra-high density warp-resistant memory module 62 1996
5,895,232 Three-dimensional warp-resistant integrated circuit module method and apparatus 9 1997
6,190,939 Method of manufacturing a warp resistant thermally conductive circuit package 6 1998
6,194,247 Warp-resistent ultra-thin integrated circuit package fabrication method 15 1998
6,205,654 Method of manufacturing a surface mount package 80 1998
6,608,763 Stacking system and method 36 2000
6,919,626 High density integrated circuit module 71 2001
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6,806,120 Contact member stacking system and method 7 2002
6,572,387 Flexible circuit connector for stacked chip module 72 2002
7,066,741 Flexible circuit connector for stacked chip module 33 2003
 
ROUND ROCK RESEARCH, LLC (19)
5,286,679 Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer 238 1993
6,342,731 Vertically mountable semiconductor device, assembly, and methods 10 1997
6,634,098 Methods for assembling, modifying and manufacturing a vertical surface mount package 1 1999
6,265,773 Vertically mountable and alignable semiconductor device, assembly, and methods 15 1999
6,861,290 Flip-chip adaptor package for bare die 10 2000
6,512,290 Vertically mountable and alignable semiconductor device, assembly, and methods 7 2001
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6,963,128 Vertically mountable and alignable semiconductor device assembly 0 2003
7,082,681 Methods for modifying a vertical surface mount package 0 2003
7,329,945 Flip-chip adaptor package for bare die 13 2005
7,569,418 Methods for securing packaged semiconductor devices to carrier substrates 0 2005
RE43112 Stackable ball grid array package 0 2006
7,381,591 Flip-chip adaptor package for bare die 13 2006
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8,299,598 Grid array packages and assemblies including the same 0 2010
8,164,175 Stackable semiconductor device assemblies 0 2010
8,049,317 Grid array packages 0 2010
 
ENTORIAN TECHNOLOGIES INC. (8)
5,367,766 Ultra high density integrated circuit packages method 54 1993
5,446,620 Ultra high density integrated circuit packages 72 1993
5,420,751 Ultra high density modular integrated circuit package 104 1993
5,566,051 Ultra high density integrated circuit packages method and apparatus 76 1994
5,550,711 Ultra high density integrated circuit packages 95 1995
6,049,123 Ultra high density integrated circuit packages 49 1997
6,025,642 Ultra high density integrated circuit packages 50 1997
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STAKTEK GROUP L.P. (4)
5,221,642 Lead-on-chip integrated circuit fabrication method 233 1991
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5,644,161 Ultra-high density warp-resistant memory module 92 1995
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ANALOG DEVICES, INC. (3)
6,911,727 Package for sealing an integrated circuit die 10 2003
7,508,064 Package for sealing an integrated circuit die 2 2005
7,563,632 Methods for packaging and sealing an integrated circuit die 1 2007
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
5,585,600 Encapsulated semiconductor chip module and method of forming the same 38 1993
5,567,653 Process for aligning etch masks on an integrated circuit surface using electromagnetic energy 18 1994
5,608,260 Leadframe having contact pads defined by a polymer insulating film 22 1994
 
KABUSHIKI KAISHA TOSHIBA (3)
5,278,101 Semiconductor device and method for manufacturing the same 11 1992
5,616,962 Semiconductor integrated circuit devices having particular terminal geometry 45 1994
5,773,321 Semiconductor integrated circuit devices having particular terminal geometry and mounting method 6 1996
 
SAMSUNG ELECTRONICS CO., LTD. (3)
5,849,607 Process for attaching a lead frame to a semiconductor chip 8 1996
5,776,799 Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same 40 1996
5,923,957 Process for manufacturing a lead-on-chip semiconductor device package having a discontinuous adhesive layer formed from liquid adhesive 18 1997
 
APROLASE DEVELOPMENT CO., LLC (2)
6,706,971 Stackable microcircuit layer formed from a plastic encapsulated microcircuit 13 2002
7,174,627 Method of fabricating known good dies from packaged integrated circuits 2 2003
 
ENTORIAN TECHNOLOGIES L.P. (2)
5,377,077 Ultra high density integrated circuit packages method and apparatus 97 1993
5,945,732 Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package 6 1997
 
OKI SEMICONDUCTOR CO., LTD. (2)
6,336,848 Apparatus for polishing leads of a semiconductor package 2 1998
6,726,533 Method for polishing leads for semiconductor packages 0 2001
 
TESSERA, INC. (2)
7,272,888 Method of fabricating semiconductor chip assemblies 16 2002
7,454,834 Method of fabricating semiconductor chip assemblies 9 2006
 
TEXAS INSTRUMENTS INCORPORATED (2)
5,308,797 Leads for semiconductor chip assembly and method 18 1992
5,589,420 Method for a hybrid leadframe-over-chip semiconductor package 24 1995
 
AGERE SYSTEMS INC. (1)
5,607,882 Multi-component electronic devices and methods for making them 5 1994
 
ALTERA CORPORATION (1)
6,627,517 Semiconductor package with improved thermal cycling performance, and method of forming same 0 2000
 
AU OPTRONICS CORP. (1)
5,777,705 Wire bond attachment of a liquid crystal display tile to a tile carrier 10 1997
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
5,749,988 Reworkable die attachment to heat spreader 3 1994
 
DENSE-PAC MICROSYSTEMS, INC. (1)
5,313,096 IC chip package having chip attached to and wire bonded within an overlying substrate 126 1992
 
EATON CORPORATION (1)
5,369,879 Method of mounting a semiconductor device to a heat sink 11 1993
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,385,869 Semiconductor chip bonded to a substrate and method of making 120 1993
 
HITACHI, LTD. (1)
5,371,044 Method of uniformly encapsulating a semiconductor device in resin 45 1992
 
HUGHES ELECTRONICS CORPORATION (1)
6,573,124 Preparation of passivated chip-on-board electronic devices 3 1999
 
INTERSIL CORPORATION (1)
5,434,357 Reduced semiconductor size package 18 1991
 
INVENSAS CORPORATION (1)
5,567,655 Method for forming interior bond pads having zig-zag linear arrangement 22 1995
 
LG SEMICON CO., LTD. (1)
5,742,096 Lead on chip package 3 1992
 
LSI LOGIC CORPORATION (1)
5,843,809 Lead frames for trench drams 9 1996
 
MITSUI CHEMICALS, INC. (1)
5,406,124 Insulating adhesive tape, and lead frame and semiconductor device employing the tape 194 1993
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5,585,667 Lead frame for handling crossing bonding wires 20 1994
 
SIMPLETECH, INC. (1)
RE36916 Apparatus for stacking semiconductor chips 103 1998
 
TRANSPACIFIC IP LTD. (1)
5,863,805 Method of packaging semiconductor chips based on lead-on-chip (LOC) architecture 10 1996