Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 4, 1992
Issued Date -
N/A
app pub date -
Dec 12, 1989
filing date -
Aug 7, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully