Trenching techniques for forming vias and channels in multilayer electrical interconnects

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5091339
SERIAL NO

07557427

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Carey, David H Austin, TX 17 1317

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation