Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor
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United States of America Patent
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Mar 3, 1992
Grant Date -
N/A
app pub date -
Apr 17, 1989
filing date -
Apr 17, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.
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