Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
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United States of America Patent
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Mar 3, 1992
Issued Date -
N/A
app pub date -
Sep 15, 1989
filing date -
Jun 25, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An arrangement for implementing graph operations, generally, and circuit simulations in particular employing a plurality of substantially identical high speed special purpose processing elements (PE) that are flexibly interconnected through a switch to form a cluster. In addition to the processing element (PE) being programmable, the interconnection switch permits dynamically altered routing of signals between the processing elements. The processing elements include a queue unit which permits high speed asynchronous communication between the elements. Additional advantage is attained with a hierarchical arrangement where a plurality of clusters are interconnected in an n-cube arrangement, and all of the clusters communicate with a host computer.
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