Digital multiplier employing CMOS transistors
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United States of America Patent
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Mar 10, 1992
Grant Date -
N/A
app pub date -
Feb 1, 1990
filing date -
Feb 2, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital multiplier for multiplying a binary N bit multiplicand by a binary N bit multiplier. The digital multiplier comprises a plurality of AND gates in which each digit of the mutliplicand is multiplied by each digit of the multiplier. The outputs of the AND gates represent partial products which are then arranged corresponding to each digit of the multiplier. The digital multiplier further comprises a plurality of 1's counters for receiving in parallel all partial products, except the least significant digit of the multiplier, and any carries propagated from an adjacent counter, and for counting the number of '1' in the resultant values. The 1's counters output the least significant bit as the final products, and propagate the remaining bits to the next 1's counter.
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