Non-volatile memory structure
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United States of America Patent
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Mar 17, 1992
Grant Date -
N/A
app pub date -
Mar 15, 1990
filing date -
Mar 15, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A non-volatile memory circuit for use with an E.sup.2 PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory cells are connected in parallel to a volatile memory circuit via a voltage level shifter circuit for writing operations, and via twin mixed PMOS and NMOS transistors for reading operations. With the combined complementary non-volatile memory cells and the twin mixed pairs of transistors, the stored information is retained in the event that one of the memory cells fails.
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