US Patent No: 5,102,827

Number of patents in Portfolio can not be more than 2000

Contact metallization of semiconductor integrated-circuit devices

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Abstract

In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
AGERE SYSTEMS INC.ALLENTOWN, PA2639
AT&T BELL LABORATORIESMURRAY HILL, NJ3372

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Min-Liang Hsin-chu, TW 36 627
Leung, Chung W Orlando, FL 8 195

Cited Art

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS INCORPORATED (3)
4,788,160 Process for formation of shallow silicided junctions 68 1987
4,897,703 Recessed contact bipolar transistor and method 19 1988
4,877,755 Method of forming silicides having different thicknesses 46 1988
 
ADVANCED MICRO DEVICES, INC. (2)
4,709,467 Non-selective implantation process for forming contact regions in integrated circuits 8 1986
4,782,380 Multilayer interconnection for integrated circuit structure having two or more conductive metal layers 126 1987
 
BELL TELEPHONE LABORATORIES, INCORPORATED (2)
4,502,209 Forming low-resistance contact to silicon 63 1983
4,535,532 Integrated circuit contact technique 14 1984
 
NATIONAL SEMICONDUCTOR CORPORATION (2)
4,398,335 Multilayer metal silicide interconnections for integrated circuits 43 1980
4,361,599 Method of forming plasma etched semiconductor contacts 38 1981
 
AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. (1)
4,873,204 Method for making silicide interconnection structures for integrated circuit devices 68 1988
 
HITACHI, LTD. (1)
4,701,349 Semiconductor integrated circuit device and method of producing the same 47 1985
 
INMOS CORPORATION (1)
4,784,973 Semiconductor contact silicide/nitride process with control for silicide thickness 103 1987
 
MOTOROLA, INC. (1)
4,319,395 Method of making self-aligned device 60 1979
 
SIEMENS AKTIENGESELLSCHAFT (1)
4,783,248 Method for the production of a titanium/titanium nitride double layer 49 1987

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
APPLIED MATERIALS, INC. (9)
5,877,087 Low temperature integrated metallization process and apparatus 34 1995
6,139,697 Low temperature integrated via and trench fill process and apparatus 69 1997
6,605,531 Hole-filling technique using CVD aluminum and PVD aluminum integration 0 1998
6,355,560 Low temperature integrated metallization process and apparatus 6 1998
6,726,776 Low temperature integrated metallization process and apparatus 4 1999
6,207,558 Barrier applications for aluminum planarization 36 1999
6,458,684 Single step process for blanket-selective CVD aluminum deposition 8 2000
6,368,880 Barrier applications for aluminum planarization 13 2001
6,743,714 Low temperature integrated metallization process and apparatus 1 2002
 
KABUSHIKI KAISHA TOSHIBA (2)
5,208,173 Method of manufacturing non-volatile semiconductor memory device 9 1991
5,244,835 Method of making contact electrodes of polysilicon in semiconductor device 37 1991
 
MICRON TECHNOLOGY, INC. (2)
5,372,956 Method for making direct contacts in high density MOS/CMOS processes 6 1993
6,683,357 Semiconductor constructions 0 2002
 
NEC ELECTRONICS CORPORATION (2)
5,571,753 Method for forming a wiring conductor in semiconductor device 6 1995
5,620,926 Method for forming a contact with activation and silicide forming heat treatment 13 1995
 
TEXAS INSTRUMENTS INCORPORATED (2)
5,283,203 Self-aligned contact process for complementary field-effect integrated circuits 15 1992
5,444,018 Metallization process for a semiconductor device 40 1993
 
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY (2)
5,420,067 Method of fabricatring sub-half-micron trenches and holes 27 1993
5,459,099 Method of fabricating sub-half-micron trenches and holes 75 1994
 
UNITED MICROELECTRONICS CORP. (2)
5,661,081 Method of bonding an aluminum wire to an intergrated circuit bond pad 11 1994
5,734,200 Polycide bonding pad structure 20 1997
 
BAXTER INTERNATIONAL INC. (1)
5,843,035 Air detector for intravenous infusion system 16 1996
 
LG SEMICON CO., LTD. (1)
5,607,884 Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film 41 1994