Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5104820
SERIAL NO

07720025

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.

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Patent Owner(s)

Patent OwnerAddress
APROLASE DEVELOPMENT CO LLC2711 CENTERVILLE ROAD SUITE 400 WILMINGTON DE 19808

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Go, deceased Tiong C late of El Toro, CA 1 275
Minahan, Joseph A Simi Valley, CA 7 470
Shanken, Stuart N Laguna Niguel, CA 6 643

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