Method of establishing an interconnection level on a semiconductor device having a high integration density

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United States of America Patent

PATENT NO 5106781
SERIAL NO

07611388

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Abstract

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Method of manufacturing a semiconductor device in which a first conductive, aluminium containing layer (15) is deposited with a low step coverage process over an insulating layer (11) with contact openings (12), in which a second conductive layer (16) is deposited with a high step coverage so as to fill depressed parts of the first conductive layer at the area of the contact openings. The second conductive layer (16) then is substantially eliminated outside the depressed parts and interconnection lines (18) are formed in the first conductive layer. According to the invention the second conductive layer is deposited by D.C. bias sputtering of an aluminium alloy at a substrate temperature which is sufficiently high to obtain a sufficient surface mobility of the deposited alloy. Therefore a planarized layer of the second conductive material (18) is obtained.

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Patent Owner(s)

Patent OwnerAddress
U S PHILIPS CORPORATIONNEW YORK NY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Penning, De Vries Rene G M Eindhoven, NL 2 70

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