Memory management unit capable of expanding the offset part of the physical address

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United States of America Patent

PATENT NO 5109334
SERIAL NO

07262861

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Abstract

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A memory management unit in which logical addresses are translated into physical addresses is provided that comprises a segment register section that is composed of a plurality of segment registers; a segment address decoder for selecting a desired segment register in the segment register section; and an effective-address selection register from which an effective address for the desired segment register is fed to the segment address decoder. A part of the logical address is used as the effective address and the remaining part of the logical address is used as an expanded part of the physical address.

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Patent Owner(s)

Patent OwnerAddress
SHARP KABUSHIKI KAISHA 22-22 NAGAIKE-CHO ABENO-KU OSAKA 545 JAPANNot Provided

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kamuro, Setsufumi Matsudo, JP 19 210

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