Mask alignment and measurement of critical dimensions in integrated circuits

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United States of America Patent

PATENT NO 5109430
SERIAL NO

07604390

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Abstract

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A method for determining alignment and critical dimensions of regions formed on a semiconductor structure during one or more process steps includes the steps of defining a pattern A at a first location on the semiconductor device during a process step, defining a second independent pattern B at the first location on the semiconductor structure during another process step, acquiring an image of the combination A and B of both the first and second patterns, filtering that image to attenuate higher spatial frequencies while preserving lower spatial frequencies, and comparing the sign result of the filtered image with the sign result of a stored image of the individual patterns to determine alignment errors. In the preferred embodiment the step of filtering includes taking the Laplacian of Gaussian convolution of the image and saving the sign of the result. The comparison between the filtered image and the stored image uses the correlation function for the filtered images. Special circuitry is disclosed for performing the method rapidly enough to enable commercial applications.

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Patent Owner(s)

Patent OwnerAddress
SCHLUMBERGER TECHNOLOGIES INCSAN JOSE CALIFORNIA 95110-1397

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Crossley, P A Palo Alto, CA 2 87
Nishihara, H Keith Los Altos, CA 45 2990

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