Importance

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Abstract

A demodulating apparatus comprises a frequency detector for performing a frequency-detection on a digital modulation signal to acquire a detection signal, a clock generator for generating a clock signal, and a discrimination circuit for sampling a voltage level of the detection signal from the frequency detector at a clock timing of the clock signal from the clock generator, and converting the sampled voltage level into digital data, which is set to have one of first and second logic values on the basis of a reference voltage LDC. Particularly, the discrimination circuit includes a control circuit for comparing the voltage level En sampled at a clock timing, voltage level En-1 sampled at a timing one clock earlier than En and voltage level En-2 sampled at a timing two clock earlier than En, with first and second threshold voltages LA and LB respectively higher and lower than the reference voltage LDC, and controlling the clock generator to synchronize the phase of the clock signal with the detection signal when it is detected from the comparison that anyone of first and second conditions is satisfied where the first condition is En-2

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First Claim