Single event upset hardening CMOS memory circuit
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United States of America Patent
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-
May 5, 1992
Grant Date -
N/A
app pub date -
Nov 6, 1990
filing date -
Nov 6, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.
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