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Abstract

A computer memory includes K hard memory locations, hereinafter HMLs, each HML having M counters. A reference address element stores a reference address sequence of N bits. A data register stores data as a sequence of M integers. The memory has a processor system for determining a subset of HMLs to access for each reference address during read and write operations. For each HML, the processor system receives a subset of the reference address bits equal in number to q. The subset of reference address bits is chosen by selecting, for each HML, q integers between 1 and N as selected coordinates, hereinafter SCs, each SC corresponding to a bit position within the reference address, and for each SC for each HML, assigning a 0 or 1 as an assigned value for that SC. The processor system then stores the SCs and the assigned values and, for each of the SCs for each of the HMLs, compares the assigned value for the SC with the value of the corresponding bit in the reference address bits. The processor system then accesses those HMLs for which the assigned values for all SCs are identical with the corresponding bits in the subset of the reference address bits. During a write, the processor system combines data in the data register with any data already located in the M counters in each of the accessed HMLs, the M counters in each of the accessed HMLs being used for storing the combined data. The memoryy also has an accumulator system made up of a set of M accumulators with the i.sup.th accumulator coupled to receive data from the i.sup.th counter, for each accessed HML, so that each of the accumulators accumulates integers from the counters, receiving one integer from the corresponding counter for each accessed HML, thereby obtaining a value Vi in the i.sup.th accumulator. The accumulator system can then be used for outputting data corresponding to the values in the accumulators.

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