Importance

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Abstract

A local memory fast selection apparatus is utilized in a data processing system having a plurality of memory resources including a local memory and addressing by logical/virtual addresses which are converted into physical addresses. The local memory fast selection apparatus comprises a memory management unit (MMU) for converting a logical address in a physical address and for generating a destination code which identifies the memory resource, and an auxiliary memory having the same number of addressable locations of the MMU and loaded together with the MMU. The auxiliary memory has a physical address corresponding to the logical address by which the MMU is addressed and a destination code. The auxiliary memory stores a bit decoded from the destination code and selects a predetermined memory resource. Thus, the auxiliary memory and the MMU can be read out together with the same logical address in order to jointly obtain a physical address from the MMU and a selection signal of the predetermined memory resource from the auxiliary memory without any delay caused by decoding operations.

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First Claim