Stacked configuration for integrated circuit devices

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United States of America Patent

PATENT NO 5117282
SERIAL NO

07604883

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A stacked packaging assembly for a plurality of integrated circuit devices employs a web of flexible interconnect material folded into a `layered` arrangement of parallel web fingers onto which a plurality of integrated circuit devices are surface-mounted. The leads of the integrated circuit devices are attached to interconnect links of the flexible interconnect web. A plurality of heat sink plates are interleaved with the folded web fingers of the stack, so as to engage the integrated circuit devices mounted on the web fingers. The heat sink plates are retained by thermally conductive spacer blocks along their edges. The spacer blocks are clamped together in a compact laminate structure, so as to form a rigid support which relieves mechanical stresses at the folds of the web fingers.

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Patent Owner(s)

  • INTERSIL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Salatino, Matthew M Satellite Beach, FL 19 1679

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