Importance

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Abstract

To generate quickly the several carry signals in a full adder circuit (for example a 40-bit circuit), the circuit is divided into a plurality of sub-circuits of a first type, in which complementary imaginary carry signals are generated parallel to each other. Carry look-ahead circuits are of a dual construction, each first carry look-ahead circuit receiving a logic '0' and each second carry look-ahead circuit receiving a login '1'. So the generated imaginary carry signals are complementary, from which the carry signal proper is selected with the aid of a multiplex switch. The multiplex switch is controlled by the carry signal generated in a preceding sub-circuit of the first type. Since a multiplex switch operates faster than 3-bit or 4-bit wide carry look-ahead circuits, which operate in parallel in groups, the carry signals are consequently generated faster.

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First Claim