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Abstract

A fault tolerant circuit and method of synchronizing multiple asynchronous input signals, such as reset signals, in a modular redundant fault-tolerant computer system in which clock signals or respective slices have a bounded skew with respect to one another. The input signal and clock signal for each slice of the system are used to produce an initial synchronization signal in each slice of a first layer of the circuit. Each initial synchronization signal is used with an inverted version of each of the slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice. The local synchronization signals for each slice are passed to a majority-voter which produces a voted output signal for the slice. The voted output signal and the clock signal for each slice are then used to produce a finally synchronized output signal for that slice. The output signals for the multiple slices are synchronized to the respectively associated slice clock signals, and to one another within the bounded skew of the slice clock signals.

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First Claim