Importance

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Abstract

An incoming data signal including so-called gaps is synchronized to a new outgoing clock signal by employing a single elastic store and a smooth write address. An elastic store write address is generated in response to an incoming clock signal and is inhibited from advancing during the gaps in the incoming data signal. A smooth clock signal is obtained by appropriately dividing the incoming clock signal by a value dependent on the duration of the gaps in a predetermined portion of the incoming data signal. The smooth clock signal is used to control a counter to generate a smooth write address. The smooth write address is supplied to a phase detector. An adjusted read address is generated in response to the new outgoing clock signal and is supplied to the elastic store and to the phase detector. A counter used to generate the adjusted read address is inhibited from advancing during intervals in which gaps are to appear in the output data signal from the elastic store. A stuff decision is made at predetermined stuff decision points which are strategically placed relative to the positions of the gaps to be inserted in the outgoing data signal so that apparent jumps in a write-read separate signal generated by phase detector do not affect the stuff decision.

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First Claim