CMOS to ECL/CML level converter
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United States of America Patent
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Jun 16, 1992
Grant Date -
N/A
app pub date -
Sep 4, 1990
filing date -
Sep 4, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A signal level converter for converting digital input signal levels to CML or ECL output signal levels upon an input signal level rise greater than an output signal level rise, includes a load resistor having first and second terminals. A current path is disposed between the first terminal of the load resistor and a first supply voltage potential. The second terminal of the load resistor is connected to a second supply voltage potential for CML or ECL output signal levels to form a digital H level. The first terminal of the load resistor forms a converter output for CML output signal levels and/or a bipolar transistor is connected as an emitter follower having a base electrode connected to the first terminal of the load resistor and an emitter electrode forming a converter output for ECL output signal levels. A current source field transistor is connected in the current path and forms a constant current source. A switching element is connected in the current path and includes at least one control field effect transistor having a gate electrode forming a converter input.
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