Importance

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Abstract

A parallel computer comprises a processor array, a router, a grid interconnection arrangement and a control circuit for controlling the elements in parallel. The processor array comprises a plurality of processors, each processor including a data generation circuit and a data receiving circuit. The data generation circuit selectively generates messages, each including an address, and data in response to data generation control signals from the control circuit. The data receiving circuit receives messages and data in response to receiver control signals from the control circuit. The router is connected to the data generation circuit and data receiving circuit of the processors in the processor array for facilitating, in response to router control signals from the control circuit, the transfer of messages between said processors in the array in accordance with the respective addresses. The grid interconnection circuit interconnects the data generation means and receiving means of each of said processors with data receiving means and data generation means of proximate processors in the array in the form of a grid to facilitate the transfer of data between each processor and at least one of said proximate processors contemporaneously in response to grid transfer control signals from the control circuit.

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First Claim