Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor
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United States of America Patent
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Jun 23, 1992
Grant Date -
N/A
app pub date -
Apr 25, 1991
filing date -
Jun 19, 1990
priority date (Note) -
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status (Latency Note)
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Abstract
A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.
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