Circuit having a delay line for use in a data processing system or logic system
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United States of America Patent
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-
Jun 30, 1992
Grant Date -
N/A
app pub date -
Oct 5, 1989
filing date -
Oct 5, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A circuit for generating signals in a data processing system has a passive delay line and logic gates connected to the output taps of the delay line. Isolation resistors are connected between the output taps and the logic gates in order to substantially reduce signal reflections in the signal path within the delay line that are caused by the input capacitance of the logic gates.
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