Flash EEPROM array with paged erase architecture

United States of America Patent

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Jun 30, 1992
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N/A
app pub date
Oct 23, 1989
filing date
Oct 23, 1989

priority date (Note)
Expired

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Abstract

A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.

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Patent Owner(s)

Patent Owner	Address
CYPRESS SEMICONDUCTOR CORPORATION	198 CHAMPION COURT SAN JOSE CA 95134

International Classification(s)

H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Montalvo, Antonio J	San Francisco, CA	8	525
Van, Buskirk Michael A	San Jose, CA	71	2539

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Flash EEPROM array with paged erase architecture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

07426601

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PATENT NO	5126808
SERIAL NO	07426601
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07426601

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