Pipeline bus having registers and selector for real-time video signal processing
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United States of America Patent
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-
Jun 30, 1992
Grant Date -
N/A
app pub date -
Jul 23, 1990
filing date -
Sep 29, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A pipeline bus having a plurality of slots in a backplane for receiving functional modules. A bus line is connected between the slots. A register and a selector are provided between each two adjacent slots. An image signal and a sync signal are transmitted from upper to lower slots in synchronism with the clock signal. The selectors output a signal either from the register or from the associated functional module to the register which is downstream.
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