US Patent No: 5,126,966

Number of patents in Portfolio can not be more than 2000

High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs

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Abstract

A stimulus engine for a logic simulation system is used to interpret a stimulus language and generate test patterns as input to a logic simulator. The stimulus language allows a large test pattern set to be represented as a program. Special purpose hardware interprets this program and generates a sequence of input/output events to the logic simulator. The program interpretation is performed while the logic simulation is executing. Special purpose hardware is used to insure that the stimulus engine is able to generate the input/output events at a rate which does not slow down the logic simulator.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MENTOR GRAPHICS CORPORATIONWILSONVILLE, OR822

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fazakerly, William Saratoga, CA 3 144
Hafeman, Dan R Sunnyvale, CA 3 144
Loesch, William Hillsborough, CA 4 63

Cited Art

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
4,306,286 Logic simulation machine 172 1979
4,656,580 Logic simulation machine 111 1982
4,594,677 System for detecting and diagnosing noise caused by simultaneous current switching 19 1983
 
MENTOR GRAPHICS CORPORATION (3)
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4,744,084 Hardware modeling system and method for simulating portions of electrical circuits 129 1987
 
NEC CORPORATION (3)
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4,725,975 Logic simulator operable on level basis and on logic block basis on each level 48 1986
4,747,102 Method of controlling a logical simulation at a high speed 32 1986
 
CIRRUS COMPUTERS LTD. (1)
4,601,032 Test-generation system for digital circuits 33 1983
 
DAISY/CADNETIX INC., A CORP. OF COLORADO (1)
4,751,637 Digital computer for implementing event driven simulation algorithm 27 1984
 
DATA I/O CORPORATION (1)
4,571,724 System for testing digital logic devices 25 1983
 
ETA SYSTEMS, INC. (1)
4,791,578 Logic gate system design 18 1986
 
GENERAL DYNAMICS DECISION SYSTEMS, INC. (1)
4,587,625 Processor for simulating digital structures 66 1983
 
GRUMMAN AEROSPACE CORPORATION (1)
4,316,259 Programmable function generator 11 1980
 
HITACHI, LTD. (1)
4,342,093 Method of digital logic simulation 51 1980
 
INTERNATIONAL COMPUTERS LIMITED (1)
4,644,487 Method and apparatus for verifying the design of digital electronic components 32 1984
 
INVESTMENT PARTNERS OF AMERICA, L.P. (1)
4,656,632 System for automatic testing of circuits and systems 63 1983
 
MOTOROLA, INC. (1)
4,821,173 Wired "OR" bus evaluator for logic simulation 13 1988
 
NCR CORPORATION (1)
4,628,471 Digital system simulation method and apparatus having two signal-level modes of operation 15 1984
 
RANK XEROX SA (1)
4,622,647 System for the automatic testing of printed circuits 45 1983
 
SCHLUMBERGER SYSTEMS AND SERVICES, INC. (1)
4,763,288 System for simulating electronic digital circuits 37 1985
 
SHARP KABUSHIKI KAISHA (1)
4,775,950 Logic simulation system 45 1985

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (19)
5,680,583 Method and apparatus for a trace buffer in an emulation system 67 1994
5,661,662 Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation 66 1995
5,657,241 Routing methods for use in a logic emulation system 36 1995
5,612,891 Hardware logic emulation system with memory capability 59 1995
5,819,065 System and method for emulating memory 38 1996
5,822,564 Checkpointing in an emulation system 25 1996
5,841,967 Method and apparatus for design verification using emulation and simulation 66 1996
5,920,712 Emulation system having multiple emulator clock cycles per emulated clock cycle 44 1996
5,884,066 Method and apparatus for a trace buffer in an emulation system 17 1997
5,960,191 Emulation system with time-multiplexed interconnect 74 1997
5,970,240 Method and apparatus for configurable memory emulation 45 1997
6,058,492 Method and apparatus for design verification using emulation and simulation 31 1998
6,377,912 Emulation system with time-multiplexed interconnect 60 1999
7,738,398 System and method for configuring communication systems 0 2004
7,721,036 System and method for providing flexible signal routing and timing 0 2005
7,640,155 Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications 4 2005
7,606,697 System and method for resolving artifacts in differential signals 0 2005
7,440,866 System and method for validating an input/output voltage of a target system 2 2005
7,555,424 Method and apparatus for rewinding emulated memory circuits 0 2006
 
SYNOPSYS, INC. (9)
5,625,580 Hardware modeling system and method of use 41 1994
5,691,911 Method for pre-processing a hardware independent description of a logic circuit 7 1995
5,680,318 Synthesizer for generating a logic network using a hardware independent description 3 1995
5,661,661 Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof 15 1995
5,530,841 Method for converting a hardware independent user description of a logic circuit into hardware components 25 1995
5,748,488 Method for generating a logic circuit from a hardware independent user description using assignment conditions 10 1995
5,737,574 Method for generating a logic circuit from a hardware independent user description using mux conditions and hardware selectors 1 1995
6,058,252 System and method for generating effective layout constraints for a circuit design or the like 41 1997
6,148,275 System for and method of connecting a hardware modeling element to a hardware modeling system 1 1997
 
VERISITY DESIGN, INC. (4)
6,421,251 Array board interconnect system and method 26 1998
6,134,516 Simulation server system and method 84 1998
6,026,230 Memory simulation system and method 72 1998
6,389,379 Converification system and method 121 1998
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,649,164 Sets and holds in virtual time logic simulation for parallel processors 24 1994
6,975,965 System and method for heuristically optimizing a large set of automated test sets 2 2004
 
MICROSOFT CORPORATION (2)
6,449,659 System for instance customization with application independent programming of controls 28 1997
6,718,534 System for application independent programming of controls 6 2000
 
QUICKTURN DESIGN SYSTEMS, INC. (2)
5,812,414 Method for performing simulation using a hardware logic emulation system 42 1996
5,796,623 Apparatus and method for performing computations with electrically reconfigurable logic devices 33 1996
 
VERSITY DESIGN, INC. (2)
6,009,256 Simulation/emulation system and method 102 1997
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ALTERA CORPORATION (1)
8,000,954 FPGA emulation system 0 2006
 
ARKOS, INC. (1)
5,923,865 Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing 10 1995
 
AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. (1)
6,421,823 Bidirectional socket stimulus interface for a logic simulator 6 1995
 
COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P. (1)
5,353,433 Method and apparatus for organizing and analyzing timing information 12 1990
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
6,074,428 Minimizing logic by resolving "don't care" output values in a finite state machine 15 1994
 
NEC CORPORATION (1)
5,465,383 System for forming test patterns for large scale integrated circuits 3 1995
 
RPX CORPORATION (1)
5,920,490 Integrated circuit test stimulus verification and vector extraction system 37 1996
 
SUN MICROSYSTEMS, INC. (1)
5,493,672 Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution 26 1994
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,621,651 Emulation devices, systems and methods with distributed control of test interfaces in clock domains 27 1996