Importance

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Abstract

Disclosed is a divide-by-m counter for generating an ouptut clock signal having a fifty percent duty cycle from a higher frequency source clock signal having m cycles for each single cycle of the output clock signal and wherein m may be an odd or even integer number, the divide-by-m counter including a modulo binary counter for counting up to a predetermined number, circuitry for presetting the modulo binary counter by another predetermined number, counter clock selector for providing a counter clock signal to the modulo binary counter which, when m is odd, will be either an non-inverted source clock or an inverted source clock based upon the occurrence of either the HIGH or LOW intervals of the output clock, and interval defining circuitry for defining the beginning of such HIGH and LOW intervals of the output clock based upon the occurrence of a ripple carry pulse from the modulo binary counter.

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First Claim