Fabrication process for wafer alignment marks by using peripheral etching to form grooves
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United States of America Patent
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Jul 7, 1992
Issued Date -
N/A
app pub date -
Jul 19, 1991
filing date -
May 16, 1989
priority date (Note) -
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status (Latency Note)
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Abstract
A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.
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