Clamping circuit for data transfer bus
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United States of America Patent
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-
Jul 7, 1992
Grant Date -
N/A
app pub date -
May 22, 1989
filing date -
May 22, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A high speed computer data transfer system includes a transistor diode clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. Also, body effect upon the clamping circuit is lowered. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.
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