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Abstract

A phase lock loop for a digital input signal has a phase detector, a loop filter, a digital voltage controlled oscillator (VCO), an initial phase difference calculator, a center frequency difference calculator and an input buffer memory. In an initial training mode prepared in the PLL operation, an optimum initial phase and an optimum center frequency of the VCO to complete a lock-in state is searched for the input signal stored in the buffer memmory. By estimating the initial phase difference and the center frequency difference between the input signal and the VCO output with repetative kick-offs in calculators, optimum values mentioned above are obtained. In a normal operation mode as a second mode in which the PLL operates normally as a conventional PLL, a phase lock operation between the VCO outut as the reference signal and the input signal in the buffer memory is carried out after the PLL is kicked off with the optimum initial phase and the optimum center frequency determined in the initial training mode.

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