Linear chain of parallel processors and method of using same
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United States of America Patent
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Jul 7, 1992
Grant Date -
N/A
app pub date -
Jun 1, 1987
filing date -
Jun 1, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for processing data matrices such as images and spatially related data includes a plurality of neighborhood processing units connected in a linear chain with direct data communication links between adjacent processing units. A sequence of instructions are sent to the processing units by a single controller, where all neighborhood processing units in the system receive the same instruction at any given cycle in the instruction sequence. The width of the data matrix array is the same as a number of processors, so that there is one processor per column in the data matrix. The memory associated with each processor is external and large enough to hold the entire image or data matrix. The processors are able to operate arithmetically in a serial or parallel mode, where an efficient means is provided to transpose 8.times.8 bit submatrices between the two modes. An indirect addressing means is provided which operates on byte-wide memories external to the processing unit.
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