Signal delay circuit for minimizing the delay time dependence on power supply voltage variation
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United States of America Patent
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-
Jul 14, 1992
Grant Date -
N/A
app pub date -
Dec 3, 1990
filing date -
Jul 20, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A signal delay circuit includes a driving circuit for driving an output signal with a voltage swing voltage between a supply voltage and a ground voltage. The signal delay circuit further includes a varactor load which is coupled to the output signal and has a capacitance which increases according to the supply voltage within a variation range of the supply voltage. The varactor load keeps the delay characteristic of the signal propagation circuit independent of the change of the supply voltage, thereby ensuring high speed operation and improved reliability of the CMOS semiconductor integrated circuit.
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