Importance

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Abstract

A circuit for producing an exact duty cycle for a system having a variable system clock frequency. In the calibrate phase, a waveshape with an exact duty cycle is made by ANDing two or more clock pulse trains, each of which is a multiple of the system clock frequency. This is compared against the output of a current-controlled pulse width modulator which is programmed to produce the same duty cycle. The polarity of the comparator output as a result of the error between the exact duty cycle and the one produced by the modulator increments or decrements a counter, the output of which controls a DAC, which in turn corrects the output of the modulator. After a suitable number of interations, the modulator, which is now calibrated, will reproduce the exact duty cycle. The circuit is then put into the operate mode by disabling the counter, and programming the pulse width modulator to output the desired system duty cycle.

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First Claim