Importance

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Abstract

A parallel processing computer is disclosed in which a plurality of memory elements (e.g., caches) are accessable by a plurality of processors, and in which a fixed access priority for the processors is varied periodically to reduce differences in processing times between the processors in applications where memory access conflicts occur. The variation in priority is done infrequently enough so as not to disturb the ability of the system to avoid memory access conflicts by falling into a 'lockstep' condition, in which the fixed priority combined with a selected interleaving of the memory elements produces a memory access pattern that, for certain memory strides, produces no memory access conflicts.

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First Claim