Processor array of N-dimensions which is physically reconfigurable into N-1
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United States of America Patent
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Jul 21, 1992
Issued Date -
N/A
app pub date -
May 29, 1990
filing date -
May 29, 1990
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Abstract
A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port. An intermediary connection couples selected uncoupled data signal ports from at least a first N-1 dimensional processor subarray to selected uncoupled data signal ports from at least a second N-1 dimensional processor subarray, to form selected data signal paths between selected processor cells within the at least first and second N-1 dimensional processor subarrays.
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