Self-adjusting impedance matching driver
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 28, 1992
Grant Date -
N/A
app pub date -
Jun 7, 1990
filing date -
Jun 7, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in response to circuit means that monitors the impedance match between the output of the driver and the network it drives. By enabling selectively such gates, any impedance mismatch can be minimized. The selective enablement may be done only at power up, and thereafter only if the driven network is changed substantially.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully