Electromagnetic interference suppression device
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United States of America Patent
Stats
-
Aug 4, 1992
Grant Date -
N/A
app pub date -
Mar 16, 1990
filing date -
Mar 16, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A multi-stage electromagnetic interference suppression circuit is disclosed which utilizes a diverter network, an impedance network and a clamping network. The diverter network includes a series combination of a varistor and a three terminal gas arrester to suppress incoming transient energy in both normal and common propagation modes. The clamping network serves to suppress any transient energy overshoot which is not suppressed by the diverter stage. Radio frequency interference is filtered by X and Y capacitors forming LC filters with an inductance in the impedance network.
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