Hardware interface to a high-speed multiplexed link
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United States of America Patent
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Aug 4, 1992
Grant Date -
N/A
app pub date -
Jul 11, 1990
filing date -
Jul 11, 1990
priority date (Note) -
Expired
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Abstract
A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.
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