Plural cache architecture for real time multitasking
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United States of America Patent
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-
Aug 25, 1992
Grant Date -
N/A
app pub date -
Nov 9, 1989
filing date -
Dec 19, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a data processor, when there is any cache memory not being activated after the whole data processor has been activated, a signal is delivered to a bus driver and then a data processing unit is connected to a system bus. During the period from when the whole data processor has been activated to when all the cache memories start to be activated, the data processing unit is connected to the system bus so that data can be transmitted/received between the data processing unit and peripheral devices.
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