Importance

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Abstract

In an integrated circuit, gold interconnect metal lines are electroplated onto plating (Pd) and barrier (TiW) layers, using patterned photoresist. The photoresist is stripped and the plating layer portions thus exposed are etched to expose field areas of the barrier layer. Next, sidewall spacers are formed along each side of the interconnect lines. The field areas of the barrier layer are then etched to isolate the gold interconnect lines. The spacers offset the amount of undercut due to isotropic etching of the TiW barrier metal layer. After etching, the sidewall spacers serve to preserve the as-deposited profile of the gold interconnect lines against breadloafing in a subsequent annealing step.

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First Claim