Semiconductor FET structures with slew-rate control

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United States of America Patent

PATENT NO 5146306
SERIAL NO

07638629

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Abstract

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Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates. Further control of the delay is gained by use of a feedback signal to increase or decrease the current in the gates.

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Patent Owner(s)

  • VLSI TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ferry, Thomas V San Jose, CA 5 102
Hsue, James S San Francisco, CA 2 51
Kawa, Jamil Santa Clara, CA 70 999
Pierce, Kerry M Fremont, CA 15 636
Walker, William G Saratoga, CA 21 269

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