Importance

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Abstract

A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.

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First Claim