Circuit arrangement for the routine testing of an interface between line terminator groups and the switching matrix network of a PCM telecommunication switching system
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United States of America Patent
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Sep 8, 1992
Grant Date -
N/A
app pub date -
Feb 8, 1991
filing date -
Mar 23, 1990
priority date (Note) -
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status (Latency Note)
Importance
Abstract
The interfaces between line terminator groups of a pair of redundant line terminator groups each comprise an interface circuit which makes it possible, by being equipped with a write-read memory, a switch-over device and a control device that controls these components, to test the interface parts belonging to an active line terminator group in a spot-check fashion during a time channel reserved for this purpose and to test the interface parts belonging to the passive line terminator group during all time channels on the basis of a respective check word mirroring.
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