Process for metallizing integrated circuits with electrolytically-deposited copper
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United States of America Patent
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Sep 29, 1992
Grant Date -
N/A
app pub date -
Sep 24, 1990
filing date -
Sep 24, 1990
priority date (Note) -
Expired
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Abstract
A masked, conformal electrodeposition process for copper metallization of integrated circuits. The process is considerably less complex than other metallization processes utilizing electrodeposition, and provides excellent step coverage for sub-micron contact openings. Full-step coverage has been obtained with the process for contact openings as small as 0.5 microns in diameter. The process begins with the blanket sputter or LPCVD deposition of a thin conductive barrier layer of a material such as titanium nitride, titanium-tungsten or nitrided titanium-tungsten. A photoresist reverse image of the maskwork that normally would be used to etch the metallization pattern on the circuitry is created on the wafer on top of the barrier layer. As an option, the reverse image of the desired metallization pattern may be created by etching a dielectric material layer such as silicon dioxide or silicon nitride, using a photoresist reverse image as a template. The wafer is then transferred to an electrolytic bath, preferably with a pH of 13.5, in which copper is complexed with EDTA molecules. Metallic copper is deposited on the barrier layer where it is not covered by photoresist. At current densities of less than 1 milliamp/cm.sup.2, the process will automatically fill contact/via openings to a uniform thickness which is independent of the depth of the opening. Following electrodeposition of the metallization layer to the desired thickness, the wafer is removed from the bath, and the photoresist or dielectric material reverse-pattern mask is stripped. At this point, an optional corrosion-resistant metal layer may be galvanically plated on the surface of the copper layer. Finally, portions of the barrier layer that were exposed by removal of the resist are then removed with either a wet or a dry etch.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| MICRON TECHNOLOGY INC | 8000 S FEDERAL WAY P O BOX 6 BOISE ID 83707-0006 |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Cathey, David A | Boise, ID | 160 | 4883 |
| Gilton, Terry L | Boise, ID | 180 | 4401 |
| Tuttle, Mark E | Boise, ID | 290 | 10704 |
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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